Over the past several decades, various demodulation algorithms have been developed for handling broadcast frequency-modulated (FM) audio and/or data transmissions. Each of these algorithms provides some level of performance that makes them particularly attractive solutions in some specific situations. The same algorithm, however, is not likely to provide an optimal solution for a wide range of operating conditions. That is, an FM demodulator generally relies on a single algorithm suited to handle the typical operating conditions that the FM demodulator is likely to face.
For example, an FM demodulator that is based on phase differencing may be implemented using a small layout (i.e., small silicon area) and may be operated without a significant amount of power consumption. Such FM demodulator, however, may have very poor receiver sensitivity and may only be practical to use it when the FM signal strength (e.g., signal-to-noise ratio (SNR) or signal-to-interference and noise ratio (SINR)) is sufficiently large.
On the other hand, an FM demodulator that is based on a phase-locked loop (PLL) scheme may need more silicon area and power consumption to implement than the FM demodulator that is based on phase differencing. However, the PLL-based FM demodulator may be able to achieve good receiver sensitivity. Like the PLL-based FM demodulator, an FM demodulator based on frequency-compressive feedback (FCF) may also provide good receiver sensitivity but also requires large silicon area and power consumption.
While a typical FM demodulation algorithm may not produce optimal performance for a wide range of operating conditions, using multiple FM demodulators, each based on a different FM demodulation algorithm, is both impractical and costly. Therefore, it is desirable to have a single FM demodulator that can provide the appropriate level of performance for a wide range of situations or operating conditions.